The present invention relates to integrated semiconductor memory devices, and more particularly to an improved memory core configuration for such memories which permits the number of bits of a memory array to be increased by increasing the number of columns or rows by any amount.
Semiconductor memory devices are well known in the art, and typically comprise a memory array or core comprising a multitude of data storage elements arranged in rows and columns of the memory array. Conventionally, the number of columns of a memory array is increased only by doubling the previous number of columns. This conventional scheme permits the use of binary counters to generate internal sequential addresses. Under this constraint the width of the memory device die cannot be matched to the maximum die size for a package. If the die height/width ratio is unacceptable, only a wider package could be used.
It is accordingly an object of the invention to provide a memory array wherein the number of bits of a memory array can be increased by increasing the number of columns or rows by any arbitrary amount.
A further object of the invention is to provide a memory array in a semiconductor chip die, wherein the number of columns can be increased in increments of the word size, and the height/width ratio of the die can be optimized.